With the advancement of modem technologies, integrated circuits having more functions and greater performance are increasingly demanded, which requires more semiconductor devices to be made for a circuit. A high degree of integration can be achieved in several ways, among which scaling semiconductor devices is the most commonly used method. Ninety (90) nm, 60 nm, and even 45 nm technologies have been used to produce very small devices having high performance. During packaging processes, two or more dies may be stacked together, and the dies may include integrated circuits having similar or completely different functions, so that both device number and functional circuit number can be increased. Typically, in order to stack more than one die into a package, the dies have to be thinned by a backside grinding process wherein the backsides or inactive sides of the dies are ground or polished until the dies are of desired thicknesses. Typically, wafers are thinned and cut into dies.
These methods have a side effect, however. Small devices, particularly devices fabricated using 90 nm technology or below, are more sensitive to stress. Not only is the performance of the devices affected, but undesired stress may also cause a malfunction of the semiconductor devices, affecting the reliability of the integrated circuit. Thinner dies, on the other hand, have increased stresses, further worsening the problem.
Conventionally, research was concentrated on reducing the stresses in dies. This includes increasing either the thickness of the dies or the thickness of the molding compound for packaging. However, due to the demand for thin dies, these methods have become less practical. Additionally, modification to packaging processes requires testing and debugging, thus increasing the cost and time to market. Functional tests may also be needed after the packaging processes, particularly on chips including stress-sensitive circuits, to ensure that integrated circuits function correctly.
Therefore, there is the need for novel approaches for reducing the effect of stress on integrated circuits.